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Cray was able to look at the failure of the STAR and learn from it. He decided that in addition to fast vector processing, his design would also require excellent all-around scalar performance.
That way when the machine switched modes, it would still provide superior performance. Additionally he noticed that the workloads could be dramatically improved in most cases through the use of registers.
Just as earlier machines had ignored the fact that most operations were being applied to many data points, the STAR ignored the fact that those same data points would be repeatedly operated on.
However, there were limitations with this approach. Registers were significantly more expensive in terms of circuitry, so only a limited number could be provided.
Instead of reading any sized vector several times as in the STAR, the Cray-1 would have to read only a portion of the vector at a time, but it could then run several operations on that data prior to writing the results back to memory.
Given typical workloads, Cray felt that the small cost incurred by being required to break large sequential memory accesses into segments was a cost well worth paying.
Since the typical vector operation would involve loading a small set of data into the vector registers and then running several operations on it, the vector system of the new design had its own separate pipeline.
Cray referred to this concept as chaining , as it allowed programmers to "chain together" several instructions and extract higher performance.
The new machine was the first Cray design to use integrated circuits ICs. Although ICs had been available since the s, it was only in the early s that they reached the performance necessary for high-speed applications.
In all, the Cray-1 contained about , gates. ICs were mounted on large five-layer printed circuit boards , with up to ICs per board.
The typical module distinct processing unit required one or two boards. In all the machine contained 1, modules in varieties. Each cable between the modules was a twisted pair , cut to a specific length in order to guarantee the signals arrived at precisely the right time and minimize electrical reflection.
Each signal produced by the ECL circuitry was a differential pair, so the signals were balanced. This tended to make the demand on the power supply more constant and reduce switching noise.
The load on the power supply was so evenly balanced that Cray boasted that the power supply was unregulated. To the power supply, the entire computer system looked like a simple resistor.
In this case, each circuit board was paired with a second, placed back to back with a sheet of copper between them. The copper sheet conducted heat to the edges of the cage, where liquid Freon running in stainless steel pipes drew it away to the cooling unit below the machine.
The first Cray-1 was delayed six months due to problems in the cooling system; lubricant that is normally mixed with the Freon to keep the compressor running would leak through the seals and eventually coat the boards with oil until they shorted out.
New welding techniques had to be used to properly seal the tubing. The only patents issued for the Cray-1 computer concerned the cooling system design.
In order to bring maximum speed out of the machine, the entire chassis was bent into a large C-shape. Speed-dependent portions of the system were placed on the "inside edge" of the chassis, where the wire-lengths were shorter.
This allowed the cycle time to be decreased to NCAR estimated that the overall throughput on the system was 4. Addressing was bit, with a maximum of 1,, bit words 1 megaword of main memory, where each word also had 8 parity bits for a total of 72 bits per word.
Smaller configurations could have 0. The main register set consisted of eight bit scalar S registers and eight bit address A registers.
These were backed by a set of sixty-four registers each for S and A temporary storage known as T and B respectively, which could not be seen by the functional units.
The vector system added another eight element by bit vector V registers, as well as a vector length VL and vector mask VM. Finally, the system also included a bit real-time clock register and four bit instruction buffers that held sixty-four bit instructions each.
The hardware was set up to allow the vector registers to be fed at one word per cycle, while the address and scalar registers required two cycles.
In contrast, the entire word instruction buffer could be filled in four cycles. The Cray-1 had twelve pipelined functional units.
The bit address arithmetic was performed in an add unit and a multiply unit. The scalar portion of the system consisted of an add unit, a logical unit, a population count , a leading zero count unit and a shift unit.
The vector portion consisted of add, logical and shift units. The floating point functional units were shared between the scalar and vector portions, and these consisted of add, multiply and reciprocal approximation units.
The system had limited parallelism. The reciprocal approximation unit could also operate in parallel, but did not deliver a true floating-point result - two additional multiplications were needed to achieve a full division.
Earlier Cray designs at CDC had included separate computers dedicated to this task, but this was no longer needed. Instead the Cray-1 included four 6-channel controllers, each of which was given access to main memory once every four cycles.
The initial model, the Cray-1A , weighed 5. The Cray-1S , announced in , was an improved Cray-1 that supported a larger main memory of 1, 2 or 4 million words.
The Cray-1M , announced in , replaced the Cray-1S. In the first standard software package for the Cray-1 was released, consisting of three main products:.
Cray Research attempted to support these sites accordingly. These software choices had influences on later minisupercomputers , also known as " crayettes ".
Other operating systems existed, but most languages tended to be Fortran or Fortran-based. Bell Laboratories , as proof of both portability concept and circuit design, moved the first C compiler to their Cray-1 non-vectorizing.
Application software generally tends to be either classified e. This was because little software was shared between customers and university customers.
The few exceptions were climatological and meteorological programs until the NSF responded to the Japanese Fifth Generation Computer Systems project and created its supercomputer centers.
Even then, little code was shared. Cray-1 at Computer History Museum.